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IDT6178S CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
Integrated Device Technology, Inc.
IDT6178S
FEATURES:
* High-speed Address to MATCH Valid time - Military: 12/15/20/25ns - Commercial: 10/12/15/20/25ns (max.) * High-speed Address Access time - Military: 12/15/20/25ns - Commercial: 10/12/15/20/25ns (max.) * Low-power consumption - IDT6178S Active: 300mW (typ.) * Produced with advanced CMOS high-performance technology * Input and output TTL-compatible * Standard 22-pin Plastic or Ceramic DIP, 24-pin SOJ * Military product 100% compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT6178 is a high-speed cache address comparator sub-system consisting of a 16,384-bit StaticRAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal. The IDT6178 features an onboard 4-bit comparator that compares RAM contents and current input data. The result is an active HIGH on the MATCH pin. The MATCH pins of several IDT6178S can be handed together to provide enabling or acknowledging signals to the data cache or processor. The IDT6178 is fabricated using IDT's high-performance, high-reliability CMOS technology. Address to MATCH and Data to MATCH times are as fast as 10ns. All inputs and outputs of the IDT6178 are TTL-compatible and the device operates from a single 5V supply. The IDT6178 is packaged in either a 22-pin, 300-mil Plastic or Ceramic DIP package or 24-pin SOJ. Military grade product is manufactured in compliance with latest revision of MILSTD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0 ADDRESS DECODE A11 16,384-BIT MEMORY ARRAY VCC GND
I/O0 - I/O3
4
CONTROL I/O
4
WE OE CLR
CONTROL
CLEAR MEMORY ARRAY
4
COMPARATOR
4
MATCH
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1994 Integrated Device Technology, Inc.
MAY 1994
DSC-1059/2
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IDT6178S CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11
DIP TOP VIEW
A0
1 2 3 4 5 6 7 8 9 10 11 12
SOJ TOP VIEW
24 23 22 21 20 S024-4 19 18 17 16 15 14 13
VCC A11 A10 A9 A8 NC
22 21 20 19 P22-1 & D22-1 18 17 16 15 14 13 12
VCC A11 A10 A9 A8
A1 A2 A3 A4 A5 NC A6 A7
CLR
I/O3 I/O2 I/O1 I/O0 MATCH
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CLR
I/O3 I/O2 I/O1 I/O0 MATCH
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OE WE
GND
OE WE
GND
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +7.0 -55 to +125 -65 to +135 -65 to +150 1.0 50 Unit V C C C W mA
PIN DESCRIPTIONS
A0-A11 I/O0-I/O3 MATCH Address Inputs Data Input/Output Match Write Enable Output Enable Clear Power Ground
2953 tbl 01
TA TBIAS TSTG PT IOUT
WE OE CLR
VCC GND
2953 tbl 04 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty.
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Military Ambient Temperature 0C to +70C -55C to +125C GND 0V 0V VCC 5.0V 10% 5.0V 10%
2953 tbl 02
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2(2) -0.5
(1)
Typ. 5.0 0 - -
Max. 5.5 0 6.0 0.8
Unit V V V V
2953 tbl 05
TRUTH TABLES(1)
NOTES: 1. VIL = -3.0V for pulse width less than 20ns, once per cycle. 2. VIH = 2.5V for clear pin.
WE
H L H X
OE
H X L X
CLR
H H H L
MATCH Valid(2) Invalid Invalid Invalid
Mode Match Cycle Write Cycle Read Cycle Clear Cycle
2953 tbl 03
CAPACITANCE (TA = 25C, f = 1MHz)
Symbol CIN CI/O Parameter Input Capacitance I/O Capacitance Condition VIN = 0V VOUT = 0V Max 8 8 Units pF pF
NOTE: 1. H = VIH, L = VIL, X = Don't care. 2. Valid Match = VOH, Valid Non-Match = VOL.
NOTE: 2953 tbl 06 1. This parameter is determined by device characterization, but is not production tested.
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IDT6178S CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
6178S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage Test Condition VCC = 5.5V, VIN = 0V to VCC Min. -- -- -- -- -- -- 2.4 2.4 Max. 10 10 0.4 0.5 0.4 0.5 -- -- Unit A A V V V V V V
2953 tbl 07
OE = VIH, VOUT = 0V to VCC
IOL = 8mA (I/O0 - I/O3) IOL = 10mA (I/O0 - I/O3) IOL = 16mA (Match) IOL = 20mA (Match)
VOH
Output High Voltage
IOH = -4mA (I/O0 - I/O3) IOH = -8mA (Match)
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
Symbol ICC1 ICC2 Parameter Operating Power Supply Current Outputs Open, VCC = Max., f = 0(2) COM'L. MIL. 6178S10 Max. 90 -- 180 -- 6178S12(1) Max. 90 110 160 180 6178S15(1) Max. 90 110 140 160 6178S20/25 Max. 90 110 140 160
Unit mA mA mA mA
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Dynamic Operating Current COM'L. Outputs Open, VCC = Max., f = fMAX(2) MIL.
NOTES: 1. Military values are preliminary only. 2. fMAX = 1/tRC, only address inputs are cycling at fMAX. f = 0 means no address inputs change.
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load AC Test Load for Match Cycle GND to 3.0V 5ns 1.5V 1.5V See Figures 2 and 3 See Figure 1
2953 tbl 09
+5V
240 MATCHOUT 128 30pF*
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Figure 1. AC Test Load for MATCH
+5V
+5V
480 DATAOUT 255 30pF*
DATAOUT 255
480
5pF*
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Figure 2. AC Test Load
Figure 3. AC Test Load
(for tOLZ, tOHZ, tWHZ, tOW) * Including scope and jig.
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IDT6178S CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
CYCLE DESCRIPTION
Match Cycle: A match cycle occurs when all control signals (OE, WE, CLR) are HIGH. At that time, data supplied to the RAM on the I/O pins is compared with the data stored at the specified address. The totem-pole match output is HIGH when there is a match at all data bits, and drives LOW if there is not a match. Write Cycle: The write cycle is conventional, occuring when WE is LOW and CLR is HIGH. OE may be either HIGH or LOW, since it is overridden by WE. The state of the Match pin is not guaranteed, but in the current implementation it continues to reflect the output of the comparator. The Match pin goes HIGH during write cycles since the data at the specified address is the same as the data (being written) at the I/Os of the RAM.
6178S10(1) Symbol Match Cycle tADM tDAM tMHO tOEM tMHW tWEM tMHCLR tMHA tMHD Address to Match Valid Data Input to Match Valid Match Valid Hold from OE -- -- 0 -- 0 -- 0 3 3 10 8 -- 10 -- 10 -- -- -- Parameter Min. Max.
Read Cycle: When WE and CLR are HIGH and OE is LOW, the RAM is in a read cycle. The state of the Match pin is not guaranteed, but in the current implementation it continues to reflect the output of the comparator. The Match pin goes HIGH during read cycles since the data at the specified address is the same as the data (being read) at the I/Os of the RAM. Clear Cycle: When CLR is asserted, every bit in the RAM is cleared to zero. If OE is LOW during a clear cycle, the RAM I/Os will be driven. However, this data is not necessarily zeros, even after a considerable time. The Match pin is enabled, but its state is not predicable.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
6178S12 Min. -- -- 0 -- 0 -- 0 3 3 Max. 12 11 -- 12 -- 12 -- -- -- 6178S15 Min. -- -- 0 -- 0 -- 0 3 3 Max. 15 13 -- 15 -- 15 -- -- -- 6178S20 Min. -- -- 0 -- 0 -- 0 3 3 Max. 20 15 -- 20 -- 20 -- -- -- 6178S25 Min. -- -- 0 -- 0 -- 0 3 3 Max. 25 15 -- 20 -- 20 -- -- -- Unit ns ns ns ns ns ns ns ns ns
2953 tbl 10
OE HIGH to Match Valid Match Valid Hold from WE WE HIGH to Match Valid Match Valid Hold from CLR
Match Valid Hold from Address Match Valid Hold from Data
NOTE: 1. 0C to +70C temperature range only.
TIMING WAVEFORM OF MATCH CYCLE(1)
ADDRESS tADM tMHA
OE
tOEM tMHO
WE
tWEM tMHW
CLR
tMHCLR I/O1-4 VALID READ DATAOUT VALID MATCH DATAIN tDAM MATCH
NO MATCH MATCH
tMHD MATCH VALID MATCH
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NOTE: 1. It is not recommended to let address and data input pins float while MATCH pin is active.
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IDT6178S CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
6178S10(1) Symbol Read Cycle tRC tAA tOE tOH tOLZ
(2) (2)
6178S12 Min. 12 -- -- 3 2 -- Max. -- 12 8 -- -- 7
6178S15 Min. 15 -- -- 3 2 -- Max. -- 15 10 -- -- 9
6178S20/25 Min. 20/25 -- -- 3 2 -- Max. -- 20/25 15 -- -- 12 Unit ns ns ns ns ns ns
2953 tbl 11
Parameter Read Cycle Time Address Access Time Output Enable Access Time Output Hold from Address Change Output Enable to Output in Low-Z Time Output Disable to Output in High-Z Time
Min. 10 -- -- 3 2 --
Max. -- 10 7 -- -- 6
tOHZ
NOTES: 1. 0C to +70C temperature range only. 2. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA tOH
OE
tOLZ DATAOUT
(3)
tOE
tOHZ (3) DATAOUT VALID
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TIMING WAVEFORM OF READ CYCLE NO. 2(1,2)
tRC ADDRESS
tAA tOH DATAOUT PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
DATAOUT VALID
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NOTES: 1. WE is HIGH for Read Cycle. 2. Output enable is continuously active, OE is LOW. 3. Transition is measured 200V from steady state.
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IDT6178S CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
6178S10(1) Symbol Write Cycle tWC tAW tAS tWP tWR tDW tDH tWHZ
(2)
6178S12 Min. 12 10 0 10 0 8 0 -- 0 Max. -- -- -- -- -- -- -- 6 --
6178S15 Min. 15 12 0 12 0 10 0 -- 0 Max. -- -- -- -- -- -- -- 7 --
6178S20/25 Min. 20 14 0 14 0 12 0 -- 0 Max. -- -- -- -- -- -- -- 9 -- Unit ns ns ns ns ns ns ns ns ns
2953 tbl 12
Parameter Write Cycle Time Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold from Write Time Write Enable to Output in High-Z Output Active from End-of-Write
Min. 10 8 0 8 0 6 0 -- 0
Max. -- -- -- -- -- -- -- 5 --
tOW(2)
NOTES: 1. 0C to +70C temperature range only. 2. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
TIMING WAVEFORM OF WRITE CYCLE(1,3)
tWC ADDRESS tAW tAS tWP tWR
WE
tWHZ DATAOUT
(2) (4)
tOW
(4)
(2)
tDW DATAIN
(4)
tDH
(4)
DATAIN VALID
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NOTES: 1. WE must be HIGH during all address transitions. 2. During this period, I/O pins are in the output state and the input signals must not be applied. 3. OE is HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse is the specified tWP. 4. Transition is measured 200mV from steady state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
6178S10(1) Symbol Clear Cycle tCLPW(2) tCLRC tPOCL(3) tWECL Parameter Min. 12 5 50 5 Max. -- -- -- -- 6178S12 Min. 15 5 60 5 Max. -- -- -- -- 6178S15 Min. 20 5 80 5 Max. -- -- -- -- 6178S20/25 Min. 25 5 100 5 Max. -- -- -- -- Unit ns ns ns ns
2953 tbl 13
CLR Pulse Width CLR HIGH to WE LOW
Power on Reset
WE HIGH to Clear HIGH
NOTES: 1. 0C to +70C temperature range only. 2. Recommended duty cycle of 10% maximum. 3. This parameter guaranteed with AC load (Figure 3) by device characterization, but is not production tested.
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IDT6178S CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF CLEAR CYCLE
tCLPW
CLR
tWECL tCLRC
WE
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POWER ON RESET TIMING
tPOCL VCC
CLR
tCLRC
WE
tWECL
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ORDERING INFORMATION
IDT 6178 Device Type S Power XX Speed X Package X Process/ Temperature Blank B Commercial (0C to +70C) Military (-55C to +125C, Compliant to MIL-STD-883, Class B) 300 mil Plastic DIP (P22-1) 300 mil Small Outline, J bend (SO24-4) 300 mil Ceramic DIP (D22-1) Commercial only Speed in nanoseconds
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P Y D 10 12 15 20 25
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